1. Field of the Invention
The present invention relates to a structure of a nonvolatile semiconductor memory device, enabling electrical programming/erasing of data and storage of information even when the power is off.
2. Description of the Background Art
In resent years, digital communication networks using portable information communication terminals such as a cellular phone or Internet have been developed, and nonvolatile semiconductor memory devices are widely used in such portable terminals as memory devices enabling nonvolatile storage of information.
One example of such nonvolatile semiconductor memory devices is an electrically programmable flash memory in which stored data can be electrically erased collectively for a group of a predetermined number of bits.
FIG. 9 is a schematic block diagram showing a configuration of a conventional nonvolatile semiconductor memory device 100.
Referring to FIG. 9, nonvolatile semiconductor memory device 100 includes a ROM (Read Only Memory) therein, a CPU 8 for controlling programming and erasing operations in response to a program code held in the ROM and a command signal applied from an external source, a high voltage generating circuit for programming/erasing 10 for generating a high voltage for programming and erasing from an external power potential (not shown), and a memory cell array 120.
Memory cell array 120 includes memory blocks 120-1 to 120-n formed in P wells electrically separated from one another. The erasing operation of nonvolatile semiconductor device 100 is performed for each of the memory blocks 120-1 to 120-n.
Nonvolatile semiconductor memory device 100 further includes an input buffer 2 for receiving from an external source an address signal ADD, a chip enable signal/CE, an output enable signal/OE, a write enable signal/WE and a reset signal/RP, WP input buffer 4 for receiving a write protect signal/WP from an external source, a WL decoder/WL driver 14 for selecting a memory block and a word line in response to a row address signal applied from input buffer 2, a data buffer 6 for transmitting/receiving a data signal DATA to/from an external source, a BL decoder/driver 16 for selecting a bit line in response to a column address applied from input buffer 2 to transmit/receive data between the selected bit line and data buffer 6, and a sense amplifier circuit 18 for reading data by detecting current flowing in the bit line at the time of a reading operation.
Memory block 120-1 includes a memory transistor MT for storing normal data arranged in rows and columns and a memory transistor MTL for lock bit holding information for protecting memory block 120-1 from programming/erasing.
Memory block 120-1 further includes a selector gate SG activated when memory block 120-1 is selected, to connect a main bit line MBLO with a sub bit line SBL.
Nonvolatile semiconductor memory device 100 is so-called NOR flash memory, the source of each memory transistor MT being connected to a common source line SL.
Nonvolatile semiconductor memory device 100 further includes a SL driver 12 for receiving a predetermined potential from high voltage generating circuit for programming/erasing 10 to set the potential of source line SL.
Sense amplifier circuit 18 includes sense amplifiers SA0 to SAn corresponding to respective bit lines, and a sense amplifier SAL for detecting current in main bit line MBLL to which lock bit memory transistor MTL is connected. Sense amplifier SAL outputs the result of the detected current to CPU 8, which determines, according to the output of sense amplifier SAL, whether the programming or erasing operation is performed for each of memory blocks 120-1 to 120-n.
Lock bit memory transistor MTL is a nonvolatile memory transistor with a floating gate, which is rewritable by an operation similar to that of normal data memory transistor MT. The state of lock bit memory transistor MTL defines whether a block may be subject to data rewriting, to provide a function of protecting the block from rewriting of data already programmed therein even when an instruction for data rewriting is executed.
Operations of a memory cell, i.e., the cell holding normal data, and a lock bit cell, i.e., the cell holding a lock bit, are described below by means of NOR memory for example.
FIG. 10 is a schematic illustrating a programming operation to a memory cell.
Referring to FIG. 10, a word line WL0 is set to 10V while word lines WL1-WL3 are set to 0V. A sub bit line SBL1 is set to 5V while a sub bit line SBL0 is set to 0V. A well in which a memory block to be programmed is formed is set to 0V and source line SL is also set to 0V.
Such settings allow a memory transistor connected to word line WL0 and sub bit line SBL1 to be selected. Electrons are injected into the floating gate of the selected memory transistor so that data xe2x80x9c0xe2x80x9d is held therein.
FIG. 11 is a schematic section view illustrating a programming operation to the selected cell in FIG. 10.
Referring to FIG. 11, a positive high voltage of approximately 10V is applied to word line WL and a positive voltage of approximately 5V is applied to sub bit line SBL, and the potentials of the P well and source line SL are set to 0V for electrons to be injected into the floating gate F from the P well and source S. The injection of electrons varies a threshold voltage Vth of the selected memory transistor to be approximately 6V or higher. This is called the programming operation.
For convenience of description, the impurity region connected to source line SL is referred to as source S and the impurity region opposite to source S with a channel region interposed therebetween is referred to as drain D.
FIG. 12 is a schematic circuit diagram illustrating a reading operation.
Referring to FIG. 12, word line WL0 is set to 3V, word lines WL1-WL3 are set to 0V and source line SL is set to 0V. The reading operation is performed by a sense amplifier connected to the sub bit line, determining whether current flows in the selected memory transistor to which word line WL0 is connected.
If the selected memory cell is in a programmed state, i.e., the state in which the threshold voltage Vth is higher than 6V, no current flows therein, which is recognized that data xe2x80x9c0xe2x80x9d is held in the selected cell. On the other hand, if the threshold voltage of the selected transistor is low, i.e., if the threshold voltage Vth is in a range of approximately 1-3V, current flows in the current path shown with a broken line in FIG. 12. In this case, it is recognized that data xe2x80x9c1xe2x80x9d is held in the memory transistor.
FIG. 13 is a schematic section view illustrating an operation of the selected memory transistor at the time of reading.
Referring to FIG. 13, gate G of the memory transistor is connected to word line WL and set to 3.0V. The drain D and source S of the memory transistor are respectively connected to sub bit line SBL and source line SL, the drain being set to 1.0V while the source being set to 0V. The potential of P well in which the memory transistor is formed is set to 0V. If electrons are injected into floating gate F and the threshold voltage Vth exceeds 6.0V, the memory transistor of the selected cell is not turned on even when the gate potential is 3.0V, avoiding current flowing from drain D to source S.
On the other hand, if only few electrons are injected into the floating gate F and the threshold voltage Vth is lower than 3.0V, current i flows from drain D to source S. The current i is detected by the sense amplifier connected to the sub bit line SBL, for reading the information in the selected cell.
FIG. 14 is a schematic circuit diagram illustrating an erasing operation of a memory cell.
Referring to FIG. 14, when the erasing operation is performed, word lines WL0-WL3 of the block to be subjected to the erasing operation are collectively set to xe2x88x9210V, while the potential of the well in which the memory block to be subjected to the erasing operation is formed is set to 10V, and source line SL is also set to 10V. Sub bit line SBL connected to the memory block subjected to the erasing operation is set open by setting the selector gate non-conductive.
In such settings, a high electric field is collectively applied to the memory transistors within the same well. Electrons are extracted from the floating gates of the memory transistors in a memory block subjected to the erasing operation, which is performed for collectively lowering the high threshold voltages Vth of the memory transistors to approximately 1-3V.
FIG. 15 is a schematic section view illustrating a potential to be set for each memory transistor in the erasing operation.
Referring to FIG. 15, gate G of the memory transistor is set to xe2x88x9210V via word line WL. Source S is set to 10V via source line SL. Drain D is set open by separating sub bit line SBL from main bit line MBL. P well is set to 10V.
Such setting of the potential allows electrons to be extracted from floating gate F into P well and source S. Thus, the threshold voltage Vth of the memory transistor is set in the erased state, i.e., in a range of 1-3V, lowered from the voltage of 6V or higher.
Conventionally, the memory transistor for lock bit is configured in a separate region from the memory array region for data storage or within the memory array region for data storage. However, in the case of providing the memory transistor for a lock bit in the region separated from the memory array region for data storage, there has been a problem that the area is increased since the well and so forth must also be separated. In spite of the same data rewriting operation of the lock bit cell and that of the memory cell, the separated regions may change the cell properties, varying, for example, the threshold voltages Vth of the memory cells after the data rewriting operation. This may result in possible reading error of either the lock bit cell or the memory cell at the time of reading.
Therefore, a number of methods have been employed to provide the lock bit cell within the memory array region, which would be advantageous in terms of the area and reliable in reading operation.
FIG. 16 is a section view illustrating a structure in which the memory cell for data storage and the lock bit memory cell are provided in the same well.
Though the section shown in FIG. 16 is a section of a column in which the lock bit memory cell is provided, the column of the memory cell for holding normal data provided adjacent thereto also has a similar sectional structure.
Referring to FIG. 16, an N well 132 is provided on a P substrate 130, and P wells134, 136 and 138 are provided in N well 132. P well 134 is a P well in which a memory cell of a block 1 is formed. P well 138 is a P well in which a memory cell of a block 2 is formed. P well 136 is a P well in which selector gates SG-L1 and SG-L2 are formed for selectively connecting main bit line MBL with the sub bit line.
Provided on the main surface of P well 134 are a memory transistor for a lock bit MTL1 and a dummy memory transistor MD arranged in the same column as memory transistor MTL1. Memory transistor MTL1 shares an N type impurity region forming source S, with dummy memory transistor MD, the N type impurity region being connected to source line SL.
Drain D1 of memory transistor MTL1 and drain D2 of dummy memory transistor MD are connected to a common sub bit line SBLL1, the sub bit line SBLL1 being coupled to main bit line MBL when the selector gate SG-L1 becomes conductive.
Thus, when an erase command or a data programming command for memory block 1 is input, selector gate SG-L1 and the gate potential of memory transistor MTL are first activated. The lock-bit state is then detected by the sense amplifier connected to main bit line MBL, for transmission to the CPU, which in turn determines whether or not the memory block corresponding to the lock bit is actually erased/programmed.
In the configuration as shown in FIG. 16, the dummy cell is connected to the same bit line as that of the lock bit cell.
It is advantageous in terms of the area that the lock bit cell is formed to have a size equal to that of the memory cell for normal data. This is because the memory cell for normal data is designed to have a size as small as permissible in order to maintain the area of the memory array to be small.
Thus, an extra column is provided in the memory block to provide the lock bit cell. A number of dummy memory cells are also provided in addition to the cell used for the lock bit. Though the dummy memory cells may be used to store information, those cells are left as unusable dummy cells since the storage of normal data therein would complicate address control or the like.
It is possible to form only the lock bit cell and no other memory cells, which would, however, cause the loss of pattern uniformity in the column having the lock bit cell. As previously described, the memory cell portion uses a transistor having a size as small as permissible, so that the breakage of the pattern uniformity may cause undesirable inconsistency in etching in the manufacturing process. Thus, the dummy cells not particularly used for storing data are provided in the column where the lock bit is provided.
However, when the dummy cells are in an over-erased state, a problem of reading error arises at the time of reading information in the lock bit cell.
FIG. 17 is a graph illustrating the over-erased state.
Referring to FIG. 17, in the memory block, the memory transistors inside thereof are collectively erased, so that the application of voltage is repeated until the threshold voltages of all the memory transistors are reduced to 3.0V or lower. However, the memory transistors have different threshold values respectively, because of respective data programmed previously. In addition, some memory transistors are more susceptible than others, in shifting of the threshold voltages.
For the reasons described above, the distribution of the threshold voltages after the erasing operation has a more or less variation even within one block. In the case where such variation is caused, the cell of which the threshold voltage Vth is 0V or lower is referred to as an over-erased cell.
In FIG. 17, the voltage distribution of the memory transistors in the over-erased state is shown in the shaded portion. The memory transistor in the over-erased state may result in a depletion mode transistor in which drain current flows even when the gate voltage is 0V.
FIG. 18 is a graph showing characteristics of the gate voltage and the drain current of the memory transistor having different threshold voltages in the erased state.
Referring to FIG. 18, if the threshold voltage is 1V or 3V, the drain current is smaller than a predetermined value when the gate voltage Vg is 0V. If the threshold voltage is 0V, however, the current equal to the predetermined value flows in the memory transistor even when the gate voltage Vg is 0V. Moreover, the memory transistor having the threshold voltage of xe2x88x921.0V causes the drain current to flow therein unless the gate voltage is set to have a potential of considerably large value in the negative side.
FIG. 19 is a circuit diagram illustrating the reading error of the lock bit.
Referring to FIG. 19, the over-erased state of the dummy cell MD-1 is discussed. When the memory transistor MTL holding lock-bit information is to be read, word line WL0 is activated while word lines WL1-WL3 are inactivated, providing a potential difference between the source line and the main bit line.
Then, current i flowing from main bit line MBLL to source line SL via sub bit line SBLL is detected. However, if the memory transistor in the over-erased state as described exists, current flows even when the gate potential is 0V in the dummy cell MD-1 which is supposed to be inactivated, so that the current i will be detected even when no current is actually flowing in memory transistor MTL.
Memory transistor MTL is recognized to be always in the erased state, i.e., the state holding data xe2x80x9c1,xe2x80x9d which wrongly permits the erasing or programming of memory block 120 according to this information.
To avoid such malfunction, when the over-erased state of the dummy cell is detected for threshold voltage Vth to be in a normal range, the operation such as reprogramming of each bit must be performed, resulting in a problem leading to increased operation time.
An object of the invention is to provide a nonvolatile semiconductor memory device with improved reliability and shortened operation time, preventing a lock bit memory cell from malfunctioning due to a dummy cell.
According to one aspect of the invention, the present invention relates to a nonvolatile semiconductor memory device including memory blocks each as a unit for collectively performing an erasing operation. Each of the memory blocks includes a plurality of normal memory cells, arranged in matrix of normal rows and normal columns, holding normal data provided from an external source, and a lock bit cell column (a column including a lock bit) arranged adjacent to at least any one of the plurality of normal columns, holding the lock bit forming permission information on programming and erasing for a memory block. The lock bit cell column includes a first field effect transistor with a floating gate, connected between a first internal node and a second internal node, holding the lock bit depending on a threshold voltage, and a second field effect transistor connected between the second internal node and a third internal node electrically isolated form the first internal node.
According to another aspect of the invention, a nonvolatile semiconductor memory device includes memory blocks each as a unit for collectively performing the erasing operation. Each of the memory blocks includes a plurality of normal memory cells, arranged in matrix of normal rows and normal columns, holding normal data provided from an external source, a plurality of word lines respectively provided corresponding to the normal rows, and a lock-bit cell column arranged adjacent to at least any one of the normal columns, holding a lock bit forming permission information on programming and erasing for the memory block. The lock-bit cell column includes first and second field effect transistors each having a control gate and a floating gate. The first field effect transistor is connected between first and second internal nodes, holding a lock bit depending on the threshold voltages, the control gate thereof being connected to any one of the plurality of word lines. The second field effect transistor is connected in parallel with the first field effect transistor, the control gate thereof being connected to a third internal node having a potential where no extraction of electrons from the floating gate occurs at the time of collective erasing of the memory block.
According to a further aspect of the invention, a nonvolatile semiconductor memory device includes memory blocks each as a unit for collectively performing the erasing operation. Each of the memory blocks includes a plurality of normal memory cells, arranged in matrix of normal rows and normal columns, holding normal data provided from an external source, and a lock-bit cell column arranged adjacent to at least any one of the plurality of the normal columns, holding a lock bit forming permission information on programming and erasing for the memory block. The lock-bit cell column includes a first field effect transistor with the floating gate, connected between a first internal node and a second internal node, holding a lock bit depending on a threshold voltage, and a second field effect transistor without a floating gate, connected in parallel with the first field effect transistor.
Thus, it is a main advantage of the present invention that the reading of the lock bit is not influenced even when the dummy cells are in the over-erased state, resulting in improved reliability of lock-bit reading and shortened operation speed.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.